The present invention relates to a communication system, a communication apparatus and an electronic appliance. The present invention can suitably be applied to a semiconductor memory apparatus adapted to receive data transmitted from an electronic appliance when it is fitted to the electronic appliance, which may typically be a digital still camera, and store them in the internal semiconductor memory.
Among semiconductor memory apparatus of the above-described type, card-shaped semiconductor memory apparatus showing a card-like profile have become popular in recent years. For example, memory stick PRO (R) is known as card-shaped semiconductor memory apparatus (see Japanese Patent Application Laid-Open Publication No. 2003-242470).
Such a card-shaped semiconductor memory apparatus is typically mounted in a digital still camera for use. As the digital still camera is operated by the user to pick up an image of an object of shooting, it executes a necessary image pickup process and transmits the video data obtained as a result of the image pickup process to the card-shaped semiconductor memory apparatus mounted in it. Then, the card-shaped semiconductor memory apparatus receives the video data transmitted from the digital still camera and stores them in the semiconductor memory in the inside.
Now, the typical configuration of card-shaped semiconductor memory apparatus will be described by referring to FIGS. 1A through 5 of the accompanying drawings. As shown in FIG. 1A, card-shaped semiconductor memory apparatus 1X has a substantially box-shaped cabinet 2X.
A plurality of belt-like terminals T (T1X through T10X) to be connected to an electronic appliance such as a digital still camera when communicating with the electronic appliance are arranged along one of the short edges of the rear surface of the cabinet 2X as shown in FIG. 1A. The belt-like terminals T are arranged in such a way that their longitudinal directions agree with the longitudinal direction of the cabinet 2X so as to be separated from each other by gaps and run in parallel with each other.
The lowermost belt-like terminal, or the first belt-like terminal T1X, of the belt-like terminals T (T1X through T10X) is connected to the ground potential level when it is connected to the electronic appliance. The second belt-like terminal T2X arranged immediately above the first belt-like terminal T1X is adapted to receive a bus state signal (which will be described in greater detail hereinafter) from the electronic appliance. The third through fifth belt-like terminals T (T3X through T5X) arranged sequentially above the second belt-like terminal T2X are adapted to receive data as input from and output data to the electronic appliance for data transmission/reception. The sixth belt-like terminal T6X arranged immediately above the fifth belt-like terminal T5X is adapted to be used when judging if the card-shaped semiconductor memory apparatus 1X is properly mounted in the electronic appliance or not.
The seventh belt-like terminal T7X arranged immediately above the sixth belt-like terminal T6X is adapted to receive data as input from and output data to the electronic appliance for data transmission/reception. The eighth belt-like terminal T8X arranged immediately above the seventh belt-like terminal T7X is adapted to receive clock signals necessary for data communication with the electronic appliance. The ninth belt-like terminal T9X immediately above the eighth belt-like terminal T8X is adapted to be used when power is supplied from the electronic appliance. The tenth belt-like terminal T10X arranged above the ninth belt-like terminal T9X is connected to the ground potential level when it is connected to the electronic appliance.
Now, referring to FIG. 2, a digital still camera in which the card-shaped semiconductor memory apparatus 1X is mounted is provided with a card insertion slot 100 through which the card-shaped semiconductor memory apparatus 1X is inserted. A plurality of terminal connecting sections 101 are arranged in the card insertion slot 100 so as to correspond to the belt-like terminals T of the card-shaped semiconductor memory apparatus 1X when the latter is inserted in the card insertion slot 100.
The card-shaped semiconductor memory apparatus 1X is inserted into the card insertion slot 100 along the longitudinal direction of the cabinet 2X using the short side thereof as leading edge. Then, as a result, the plurality of terminal connecting sections 101 arranged in the card insertion slot 100 and the corresponding belt-like terminals T of the card-shaped semiconductor memory apparatus 1X are connected to each other respectively. In this way, the card-shaped semiconductor memory apparatus 1X is mounted in the digital still camera.
As a result, the control section of the digital still camera can sequentially input the video data acquired typically by way of an image pickup process to the card-shaped semiconductor memory apparatus 1X by way of the terminal connecting sections 101 in the card insertion slot 100 and then the belt-like terminals T connected to them. At this time, the control section of the card-shaped semiconductor memory apparatus 1X causes the internal semiconductor memory to store the video data input from the digital still camera by way of the belt-like terminals T.
Now, the connection arrangement for the digital still camera and the card-shaped semiconductor memory apparatus 1X will be described in greater detail by referring to FIGS. 3 and 4 of the accompanying drawings. As shown in FIGS. 3 and 4, the digital still camera and the card-shaped semiconductor memory apparatus 1X are connected to each other by way of first through tenth connection lines L (L1 through L10).
The first connection line L1 is established when the fourth belt-like terminal T4X of the card-shaped semiconductor memory apparatus 1S and the corresponding one of the terminal connecting sections 101 on the digital still camera side are connected to each other. Similarly, the second, third and fourth connection lines L (L2 through L4) are established when the third, fifth and seventh belt-like terminals T (T3X, T5X and T7X) and the corresponding ones of the terminal connecting sections 101 on the digital still camera side are connected to each other respectively. Likewise, the fifth, sixth and seventh connection lines L (L5 through L7) are established when the second, eighth and ninth belt-like terminals T (T2X, T8X and T9X) and the corresponding ones of the terminal connecting sections 101 on the digital still camera side are connected to each other respectively. Similarly, the eighth, ninth and tenth connection lines L (L8 through L10) are established when the first, tenth and sixth belt-like terminals T (T1X, T10X, T6X) and the corresponding ones of the terminal connecting sections 101 on the digital still camera side are connected to each other respectively.
More specifically, the card-shaped semiconductor memory apparatus 1X has an interface section 200 connected to the connection lines L (L1 through L10) and conducts data communications with the digital still camera by way of the interface section 200 and then the connection lines L of the interface section 200. Similarly, the digital still camera has an interface section 300 to be connected to the connection lines L and conducts data communications with the card-shaped semiconductor memory apparatus 1X by way of the interface section 300 and then the connection lines L.
Now, the configuration of the interface section 300 of the digital still camera will be described below. A first input buffer IB1 and a first output buffer OB1 are arranged in the interface section 300 so as to be connected to the first connection line L1. The first input buffer IB1 inputs the data that is input to it from the card-shaped semiconductor memory apparatus 1X by way of the first connection line L1 to a first flip-flop circuit F1 that is arranged immediately downstream relative to it. The first flip-flop circuit F1 takes in data from the card-shaped semiconductor memory apparatus 1X by latching the data from the first input buffer IB1 at the falling edge of the clock signal supplied from clock generator 301 that is arranged in the digital still camera. On the other hand, the first output buffer OB1 is connected to a second flip-flop circuit F2. The data to be transmitted to the card-shaped semiconductor memory apparatus 1X is input to the second flip-flop circuit F2 from a predetermined circuit that is arranged immediately upstream relative to it. The second flip-flop circuit F2 latches the data input from the predetermined circuit arranged immediately upstream to it at the falling edge of the clock signal supplied from the clock generator 301 and transmits it to the card-shaped semiconductor memory apparatus 1X by way of the first output buffer OB1 and then the first connection line L1. Meanwhile, the first output buffer OB1 is designed to be switched from a data output ready state where data can be output from the second flip-flop circuit F2 to the card-shaped semiconductor memory apparatus 1X to a data output suspended state where any output of data is suspended by a high impedance or vice versa according to the first switching control signal S1 supplied from a predetermined circuit in the digital still camera.
Additionally, a second input buffer IB2 and a second output buffer OB2 are arranged in the interface section 300 so as to be connected to the second connection line L2. The second input buffer IB2 is connected to a third flip-flop circuit F3 that operates like the above described first flip-flop circuit F1. The second output buffer OB2 is connected to a fourth flip-flop circuit F4 that operates like the above described second flip-flop circuit F2. Meanwhile, the second output buffer OB2 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to not the first switching control signal S1 but the second switching control signal S2 supplied from the predetermined circuit in the digital still camera.
Additionally, a third input buffer IB3 and a third output buffer OB3 are arranged in the interface section 300 so as to be connected to the third connection line L3. The third input buffer IB3 is connected to a fifth flip-flop circuit F5 that operates like the above described first flip-flop circuit F1. The third output buffer OB3 is connected to a sixth flip-flop circuit F6 that operates like the above described second flip-flop circuit F2. Meanwhile, the third output buffer OB3 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to the second switching control signal S2 supplied from the predetermined circuit in the digital still camera.
Additionally, a fourth input buffer IB4 and a fourth output buffer OB4 are arranged in the interface section 300 so as to be connected to the fourth connection line L4. The fourth input buffer IB4 is connected to a seventh flip-flop circuit F7 that operates like the above described first flip-flop circuit F1. The fourth output buffer OB4 is connected to an eighth flip-flop circuit F8 that operates like the above described second flip-flop circuit F2. Meanwhile, the fourth output buffer OB4 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to the second switching control signal S2 supplied from the predetermined circuit in the digital still camera.
Still additionally, a fifth output buffer OB5 is connected to the fifth connection line L5 in the interface section 300 and also to a ninth flip-flop circuit F9. The ninth flip-flop circuit F9 latches the bus state signal (which will be described in greater detail hereinafter) from the predetermined circuit arranged immediately upstream to it at the falling edge of the clock signal supplied from the clock generator 301 and transmits it to the card-shaped semiconductor memory apparatus 1X by way of the fifth output buffer OB5 and then the fifth connection line L5.
Furthermore, in the interface section 300, the clock signal generated by the clock generator 301 is input to the card-shaped semiconductor memory apparatus 1X by way of a sixth output buffer OB6 and then the sixth connection line L6.
Now, the configuration of the interface section 200 of the card-shaped semiconductor memory apparatus 1X will be described below. A 21st input buffer IB21 and a 21st output buffer OB21 are arranged in the interface section 200 so as to be connected to the first connection line L1. The 21st input buffer IB21 inputs the data that is input to it from the digital still camera by way of the first connection line L1 to the 21st and 22nd flip-flop circuits F (F21 and F22) that are arranged immediately downstream relative to it. The 21st flip-flop circuit F21 is adapted to be utilized in a serial transfer mode, which will be described in greater detail hereinafter, and the 22nd flip-flop circuit F22 is adapted to be utilized in a parallel transfer mode, which will also be described in greater detail hereinafter. The 21st flip-flop circuit F21 takes in data from the digital still camera by latching the data from the 21st input buffer IB21 at the rising edge of the clock signal supplied from the clock generator 301 that is arranged in the digital still camera by way of the sixth connection line L6 and then a 26-th input buffer IB26. The 22nd flip-flop circuit F22 also takes in data from the digital still camera by latching the data from the 21st input buffer IB21 at the falling edge of the clock signal supplied from the clock generator 301 that is arranged in the digital still camera by way of the sixth connection line L6 and then the 26th input buffer IB26. On the other hand, the 21st output buffer OB21 is connected to a 23rd flip-flop circuit F23. The data to be transmitted to the digital still camera is input to the 23rd flip-flop circuit F23 from the circuit arranged immediately upstream relative to it. The 23rd flip-flop circuit F23 latches the data input from the immediately upstream circuit and transmits it to the digital still camera by way of the 21st output buffer OB21 and then the first connection line L1 at the falling edge of the clock signal supplied from the clock generator 301 of the digital still camera by way of the sixth connection line L6. Meanwhile, the 21st output buffer OB21 is designed to be switched from a data output ready state where data can be output from the 23rd flip-flop circuit F23 to the digital still camera to a data output suspended state where any output of data is suspended by a high impedance or vice versa according to the third switching control signal S3 supplied from a predetermined circuit in the card-shaped semiconductor memory apparatus 1X.
Additionally, a 22nd input buffer IB22 and a 22nd output buffer OB22 are arranged in the interface section 200 so as to be connected to the second connection line L2. The 22nd input buffer IB22 is connected to a 24th flip-flop circuit F24 that operates like the above described 22nd flip-flop circuit 22. The 22nd output buffer OB22 is connected to a 25th flip-flop circuit F25 that operates like the above-described 23rd flip-flop circuit F23. Meanwhile, the 22nd output buffer OB22 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to not the third switching control signal S3 but the fourth switching control signal S4 supplied from the predetermined circuit in the card-shaped semiconductor memory apparatus 1X.
Additionally, a 23rd input buffer IB23 and a 23rd output buffer OB23 are arranged in the interface section 200 so as to be connected to the third connection line L3. The 23rd input buffer IB23 is connected to a 26th flip-flop circuit F26 that operates like the above described 22nd flip-flop circuit 22. The 23rd output buffer OB23 is connected to a 27th flip-flop circuit F27 that operates like the above described 23rd flip-flop circuit F23. Meanwhile, the 23rd output buffer OB23 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to the fourth switching control signal S4 supplied from the predetermined circuit in the digital still camera.
Additionally, a 24th input buffer IB24 and a 24th output buffer OB24 are arranged in the interface section 200 so as to be connected to the fourth connection line L4. The 24th input buffer IB24 is connected to a 28th flip-flop circuit F28 that operates like the above described 22nd flip-flop circuit 22. The 24th output buffer OB24 is connected to a 29th flip-flop circuit F29 that operates like the above described 23rd flip-flop circuit F23. Meanwhile, the 24th output buffer OB24 is designed to be switched from a data output ready state to a data output suspended state or vice versa according to the fourth switching control signal S4 supplied from the predetermined circuit in the digital still camera.
Additionally, a 25th input buffer IB25 is arranged in the interface section 200 so as to be connected to the fifth connection line L5. The 25th input buffer IB25 inputs the data that is input to it from the digital still camera by way of the fifth connection line L5 to the 30th and 31st flip-flop circuits F (F30 and F31) that are arranged immediately downstream relative to it. The 30th flip-flop circuit F30 is adapted to be utilized in a serial transfer mode, which will be described in greater detail hereinafter, and the 31st flip-flop circuit F31 is adapted to be utilized in a parallel transfer mode, which will also be described in greater detail hereinafter. The 30th flip-flop circuit F30 is adapted to latch a bus state signal from the 25th input buffer IB25 at the rising edge of the clock signal supplied from the clock generator 301 in the digital still camera by way of the sixth connection line L6 and then the 26th input buffer IB26. The 31st flip-flop circuit F31 is adapted to latch a bus state signal from the 25th input buffer IB25 at the falling edge of the clock signal supplied from the clock generator 301 in the digital still camera by way of the sixth connection line L6 and then the 26th input buffer IB26.
Power is supplied from the digital still camera to the card-shaped semiconductor memory apparatus 1X by way of the seventh connection line L7. The voltage range of the power supply is typically between 2.7 and 3.6 V. The grounding terminal of the digital still camera and that of the card-shaped semiconductor memory apparatus 1X are connected to each other by way of the eighth and ninth connection lines L (L8 and L9). As a result, the ground level of the digital still camera agrees with that of the card-shaped semiconductor memory apparatus 1X.
An insertion/pulled out detection process is conducted to detect if the digital still camera and the card-shaped semiconductor memory apparatus 1X are connected properly or not by way of the tenth connection line L10. More specifically, line L50 that is to be connected to an end of the tenth connection line L10 is connected to a predetermined electric potential (pulled up) by way of a resistor in the interface section 300 of the digital still camera. As the card-shaped semiconductor memory apparatus 1X is connected properly to the digital still camera, the other end of the tenth connection line L10 is connected to the grounding terminal of the card-shaped semiconductor memory apparatus 1X. Thus, the electric potential of the line L50 of the interface section 300 of the digital still camera is brought to level Low at this time. Therefore, the digital still camera decides that the card-shaped semiconductor memory apparatus 1X is not connected to it if the electric potential of the line L50 is at level Hi, whereas it decides that the card-shaped semiconductor memory apparatus 1X is properly connected to it if the electric potential of the line L50 is at level Low.
Meanwhile, two modes are provided for data communications between the digital still camera and the card-shaped semiconductor memory apparatus 1X. One of the two modes is a serial transfer mode for transferring 1-bit data by utilizing only the first connection line L1. The other of the two modes is a 4-bit parallel transfer mode for transferring 4-bit data by utilizing the first through fourth connection lines L (L1 through L4).
Now, the data communication process in a serial transfer mode will be described below. When data are transmitted from the digital still camera to the card-shaped semiconductor memory apparatus 1X in a serial transfer mode, the first output buffer OB1 of the digital still camera is brought into a data output ready state by a first switching control signal S1 supplied from a predetermined circuit in the digital still camera to the first output buffer OB1 and, at the same time, the second through fourth output buffers OB (OB2 through OB4) are brought into a data output suspended state by a second switching control signal S2 supplied from the predetermined circuit to the second through fourth output buffers OB (OB2 through OB4).
At this time, in the card-shaped semiconductor memory apparatus 1X, the 21st output buffer OB21 is brought into a data output suspended state by a third switching control signal S3 supplied from a predetermined circuit in the card-shaped semiconductor memory apparatus 1X to the 21st output buffer OB21 and, at the same time, the 22nd through 24th output buffers OB (OB22 through OB24) are also brought into a data output suspended state by a fourth switching control signal S4 supplied from the predetermined circuit to the 22nd through 24th output buffers OB (OB22 through OB24).
As a result, in the digital still camera, the data output from the second flip-flop circuit F2 so as to be transmitted to the card-shaped semiconductor memory apparatus 1X is actually input to the card-shaped semiconductor memory apparatus 1X by way of the first output buffer OB1 and then the first connection line L1. At this time, in the card-shaped semiconductor memory apparatus 1X, the data input to it from the digital still camera by way of the first connection line L1 is taken in by the 21st flip-flop circuit F21 by way of the 21st input buffer IB21.
When, on the other hand, data are transmitted from the card-shaped semiconductor memory apparatus 1X to the digital still camera in a serial transfer mode, the first output buffer OB1 is brought into a data output suspended state in the digital still camera by the first switching control signal S1 supplied from a predetermined circuit of the digital still camera to the first output buffer OB1 and at the same time, the second through fourth output buffers OB (OB2 through OB4) are also brought into a data output suspended state by the second switching control signal S2 supplied from the predetermined circuit to the second through fourth output buffers OB (OB2 through OB4).
At this time, in the card-shaped semiconductor memory apparatus 1X, the 21st output buffer OB21 is brought into a data output ready state by the third switching control signal S3 supplied from a predetermined circuit in the card-shaped semiconductor memory apparatus 1X to the 21st output buffer OB21 and, at the same time, the 22nd through 24th output buffers OB (OB22 through OB24) are brought into a data output suspended state by the fourth switching control signal S4 supplied from the predetermined circuit to the 22nd through 24th output buffers OB (OB22 through OB24).
As a result, in the card-shaped semiconductor memory apparatus 1X, the data output from the 23rd flip-flop circuit F23 so as to be transmitted to the digital still camera is input to the digital still camera by way of the 21st output buffer OB21 and then the first connection line L1. At this time, in the digital still camera, the data input from the card-shaped semiconductor memory apparatus 1X by way of the first connection line L1 is taken in by the first flip-flop circuit F1 by way of the first input buffer IB1.
A data communication is conducted between the digital still camera and the card-shaped semiconductor memory apparatus 1X in a serial transfer mode only by utilizing the first connection line L1 in a manner as described above. Note that, since the maximum frequency of the clock signals generated by the clock generator 301 is 20 MHz in this case, the maximum data transfer rate between the digital still camera and the card-shaped semiconductor memory apparatus 1X is 20 Mbps.
Now, the data communication process in a 4-bit parallel transfer mode will be described below. When data are transmitted from the digital still camera to the card-shaped semiconductor memory apparatus 1X in a 4-bit parallel transfer mode, the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4) of the digital still camera are brought into a data output ready state respectively by a first switching control signal S1 and a second switching control signal S2 supplied from a predetermined circuit in the digital still camera to the first output buffer OB1 and to the second through fourth output buffers OB (OB2 through OB4).
At this time, in the card-shaped semiconductor memory apparatus 1X, the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24) are brought into a data output suspended state respectively by a third switching control signal S3 and a fourth switching control signal supplied from a predetermined circuit in the card-shaped semiconductor memory apparatus 1X to the 21st output buffer OB21 and to the 22nd through 24th output buffers OB (OB22 through OB24).
As a result, in the digital still camera, the data output respectively from the second, fourth, sixth and eighth flip-flop circuits F (F2, F4, F6 and F8) so as to be transmitted to the card-shaped semiconductor memory apparatus 1X are actually input to the card-shaped semiconductor memory apparatus 1X by way of the first, second, third and fourth output buffers OB (OB1, OB2, OB3 and OB4) and then the first, second, third and fourth connection lines L (L1, L2, L3 and L4). At this time, in the card-shaped semiconductor memory apparatus 1X, the data input to it from the digital still camera by way of the first, second, third and fourth connection lines L (L1, L2, L3 and L4) are taken in respectively by the 22nd, 24th, 26th and 28th flip-flop circuits F (F22, F24, F26 and F28) by way of the 21st, 22nd, 23rd and 24th input buffers IB (IB21, IB22, IB23 and IB24).
When, on the other hand, data are transmitted from the card-shaped semiconductor memory apparatus 1X to the digital still camera in a 4-bit parallel transfer mode, the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4) are brought into a data output suspended state in the digital still camera respectively by the first switching control signal S1 and the second switching control signal S2 supplied from a predetermined circuit of the digital still camera to the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4).
At this time, in the card-shaped semiconductor memory apparatus 1X, the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24) are brought into a data output ready state respectively by the third switching control signal S3 and the fourth switching control signal S4 supplied from a predetermined circuit in the card-shaped semiconductor memory apparatus 1X to the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24).
As a result, in the card-shaped semiconductor memory apparatus 1X, the data output from the 23rd, 25th, 27th and 29th flip-flop circuits F (F23, F25, F27 and F29) so as to be transmitted to the digital still camera are input to the digital still camera respectively by way of the 21st, 22nd, 23rd and 24th output buffers OB (OB21, OB22, OB23 and OB24) and then the first, second, third and fourth connection lines L (L1, L2, L3 and L4). At this time, in the digital still camera, the data input from the card-shaped semiconductor memory apparatus 1X by way of the first, second, third and fourth connection lines L (L1, L2, L3 and L4) are taken in by the first, third, fifth and seventh flip-flop circuits F (F1, F3, F5 and F7) by way of the first, second, third and fourth input buffers IB (IB1, IB2, 1133 and IB4).
A data communication is conducted between the digital still camera and the card-shaped semiconductor memory apparatus 1X in a 4-bit parallel transfer mode by utilizing the first through fourth connection lines L (L1 through L4) in a manner as described above. Note that, since the maximum frequency of the clock signals generated by the clock generator 301 is 40 MHz in this case, the maximum data transfer rate between the digital still camera and the card-shaped semiconductor memory apparatus 1X is 160 Mbps.
FIG. 5 of the accompanying drawings is a timing chart that can be used when data are transferred from the digital still camera to the card-shaped semiconductor memory apparatus 1X. Note that this timing chart is applicable to a write operation where data transmitted from the digital still camera are written into the card-shaped semiconductor memory apparatus 1X.
The data communication between the digital still camera and the card-shaped semiconductor memory apparatus 1X is divided into four states by a bus state signal input from the digital still camera to the card-shaped semiconductor memory apparatus 1X (and the four states are referred to as “bus state BS0”, “bus state BS1”, “bus state BS2” and “bus state BS3” so as to correspond to the timing chart).
The bus state BS0 is an idle state where no data communication takes place between the digital still camera and the card-shaped semiconductor memory apparatus 1X. When the state moves into the succeeding bus state BS1, the third switching control signal S3 and the fourth switching control signal S4 in the card-shaped semiconductor memory apparatus 1X rise to bring the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24) into a data output suspended state. Additionally, since the first switching control signal S1 and the second switching control signal S2 in the digital still camera fall 1-clock thereafter, the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4) are brought into a data output ready state.
In the bus state BS1, a predetermined command (TPC (transfer protocol command)) is transferred from the digital still camera to the card-shaped semiconductor memory apparatus 1X. The predetermined command may indicate that data are to be transferred from the digital still camera to the card-shaped semiconductor memory apparatus 1X (so as to be written in the latter) or from the card-shaped semiconductor memory apparatus 1X to the digital still camera (so as to be read from the latter).
In the instance of FIG. 5, the command indicates that data are to be transferred from the digital still camera to the card-shaped semiconductor memory apparatus 1X (so as to be written in the latter). Therefore, in the succeeding bus state BS2, data are transferred from the digital still camera to the card-shaped semiconductor memory apparatus 1X.
Subsequently, when moving into the bus state BS3, since the first switching control signal S1 and the second switching control signal S2 in the digital still camera rise 1-clock before, the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4) are brought into a data output suspended state. Then, since the third switching control signal S3 and the fourth switching control signal S4 in the card-shaped semiconductor memory apparatus 1X fall 1-clock thereafter, the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24) are brought into a data output ready state.
In the bus state BS3, firstly a busy signal is transmitted from the card-shaped semiconductor memory apparatus 1X to the digital still camera. During the period of transmission of the busy signal, the card-shaped semiconductor memory apparatus 1X executes a process including an operation of adding an error correction signal to the data received from the digital still camera and other operations. When the process is completed, the card-shaped semiconductor memory apparatus 1X transmits a ready signal to the digital still camera.
FIG. 6 of the accompanying drawings is a timing chart that can be used when data are transferred from the card-shaped semiconductor memory apparatus 1X to the digital still camera. Note that this timing chart is applicable to a read operation where data are read by the digital still camera from the card-shaped semiconductor memory apparatus 1X.
In the bus state BS1, a predetermined command is issued to indicate that data are to be transferred from the card-shaped semiconductor memory apparatus 1X to the digital still camera (so as to be read from the former).
In the instance of FIG. 6, when moving from the bus state BS1 to the bus state BS2, since the first switching control signal S1 and the second switching control signal S2 in the digital still camera rise 1-clock before, the first output buffer OB1 and the second through fourth output buffers OB (OB2 through OB4) are brought into a data output suspended state. Then, since the third switching control signal S3 and the fourth switching control signal S4 in the card-shaped semiconductor memory apparatus 1X fall 1-clock thereafter, the 21st output buffer OB21 and the 22nd through 24th output buffers OB (OB22 through OB24) are brought into a data output ready state.
In the bus state BS2, firstly a busy signal is transmitted from the card-shaped semiconductor memory apparatus 1X to the digital still camera. During the period of transmission of the busy signal, the card-shaped semiconductor memory apparatus 1X executes a preparation process for transmitting data to the digital still camera. When the preparation process is completed, the card-shaped semiconductor memory apparatus 1X transmits a ready signal to the digital still camera. As the bus state moves from the bus state BS2 to the bus state BS3 in response to the transmission of the ready signal, data are transmitted from the card-shaped semiconductor memory apparatus 1X to the digital still camera.
As described in detail, the known card-shaped semiconductor memory apparatus 1X can conduct operations of data transmission between the digital still camera at a maximum data transfer rate of 160 Mbps by utilizing a 4-bit parallel transfer mode.
However, as digital still cameras tend to use more pixels, the volume of data to be transferred from a digital still camera to a corresponding card-shaped semiconductor memory apparatus 1X tends to increase further.
As the volume of video data to be transferred increases, the time to transfer the data from the digital still camera to the card-shaped semiconductor memory apparatus 1X becomes longer. Then, as the time to transfer video data becomes longer, the time to store the video data obtained by the image shooting operation of the digital still camera completely in the card-shaped semiconductor memory apparatus 1X by turn becomes longer.
A digital still camera of the type under consideration is designed so as not to execute the next image pickup process until all the video data obtained by the current image pickup process are completely stored in the card-shaped semiconductor memory apparatus 1X. Therefore, if it takes a long time before completely storing all the video data in the card-shaped semiconductor memory apparatus 1X, the continuous image pickup performance of the digital still camera inevitably becomes low.
To avoid this problem, it is necessary to raise the data transfer rate between the digital still camera and the card-shaped semiconductor memory apparatus 1X. A conceivable technique for raising the data transfer rate may be raising the frequency of the data transfer clock (the clock signal supplied from the clock generator 301).
However, the data transfer clock has already reached to 40 MHz in the known card-shaped semiconductor memory apparatus 1X as in many other known card-shaped semiconductor memory apparatus. This means that the design of the data transmission paths of the card-shaped semiconductor memory apparatus 1X may have to be drastically revised if the frequency of the data transfer clock has to be raised further. Then, there arises problems including a high cost of the card-shaped semiconductor memory apparatus 1X.